The GPMC expansion pins are available on connector P8 pins 3-26 and provide 24-bits of I/O which can be multiplexed for a variety of purposes as shown in the table below:
Pin | Function |
---|---|
3 | GPMC_AD6/MMC1_DAT6//////GPIO1_6 |
4 | GPMC_AD7/MMC1_DAT7//////GPIO1_7 |
5 | GPMC_AD2/MMC1_DAT2//////GPIO1_2 |
6 | GPMC_AD3/MMC1_DAT3//////GPIO1_3 |
7 | GPMC_ADVN_ALE/TIMER4/GPIO2_2 |
8 | GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3 |
9 | GPMC_BE0N_CLE/TIMER5/GPIO2_5 |
10 | GPMC_WEN/TIMER6/GPIO2_4 |
11 | GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13 |
12 | GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12 |
13 | GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_CRS//GPIO0_23 |
14 | GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26 |
15 | GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15 |
16 | GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14 |
17 | GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCI_O/PR1_MII0_TXD3//GPIO0_27 |
18 | GPMC_CLK/LCD_MEM_CLK/GPMC_WAIT1/MMC2_CLK/PRT1_MII1_TXEN/MCASP0_FSR/GPIO2_1 |
19 | GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22 |
20 | GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31 |
21 | GPMC_CSN1/GPMC_CLK/MMC1_CLK/PRT1EDIO_DATA_IN6/PRT1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30 |
22 | GPMC_AD5/MMC1_DAT5//////GPIO1_5 |
23 | GPMC_AD4/MMC1_DAT4//////GPIO1_4 |
24 | GPMC_AD1/MMC1_DAT1//////GPIO1_1 |
25 | GPMC_AD0/MMC1_DAT0//////GPIO1_0 |
26 | GPMC_CSN0/GPIO1_29 |
Additional connections on connector P9 are listed below:
Pin | Function |
---|---|
12 | GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28 |
17 | SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI_O/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5 |
18 | SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4 |
19 | UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13 |
20 | UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12 |
21 | SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3 |
22 | SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2 |
41 | EVENT_INTR1/TCLKIN/CLKOUT2/TIMER7/PR1PRU0_PRUR31_16/EMU3/GPIO0_20 |
As configured here, the BeagleBone FPGA board supports multiplexed 16-bit device access with three CS lines for a total address space of 384kB. Because GPMC wait requests are not provided the bus speed will have to be reduced to accomodate the slowest device access in a single cycle.
Altering the content of the on-board SPI flash also uses SPI0. A special temporary 'pass-thru' FPGA design is required which provides a direct connection between SPI0 and the SPI Flash memory to support programming and verifying the contents of the flash chip.
A bitstream download application which uses kernel I2C and SPIDEV drivers to manage the process of configuration and programming will be provided for userland setup. Additionally, a simple C language library of support functions will be available that allows custom applications to take control of the FPGA board.